1. Field of the Invention
The present invention relates to a phase comparator employed in the data communication system, etc. and a synchronizing signal extracting device using the same and, more particularly, a phase comparator which can be synchronized with not only the continuous repetitive pulse but also the discontinuous data pulse with missing pulses since the omission of pulses is caused like the tooth missing and a synchronizing signal extracting device using the same.
2. Description of the Related Art
In the data communication, the data pulse train being sent must be interpreted without error to decode the original signal precisely. For this purpose, the synchronizing signal must be detected from the data pulse train being sent, and then the original signal must be decoded by using this synchronizing signal. In order to detect the synchronizing signal, the frequency and the phase must be caused to coincide with those of the received pulse train. In the prior art, the phase locked loop (referred to as a xe2x80x9cPLLxe2x80x9d hereinafter) circuit shown in FIG. 1 is normally employed as such detecting means.
A PLL circuit 150 shown in FIG. 1 comprises the phase comparator 151 having a comparing function for comparing a phase of the input pulse with a phase of the clock signal to output a voltage signal in accordance with the compared result and a frequency discriminating function, etc., as occasion demands, the low-frequency filter/amplifier 152 for extracting a low-frequency component by removing a high-frequency component in the voltage signal output from the phase comparator 151, and the voltage-controlled oscillator 153 for oscillating at a frequency, that responds to the voltage signal containing only the low-frequency component being output from the low-frequency filter/amplifier 152, to generate the clock signal. In this PLL circuit 150, when the phase of the clock signal being output from the voltage-controlled oscillator 153 lags behind the phase of the input pulse, the phase comparator 151 detects this lag and also increases the voltage signal in accordance with this detected result to increase the frequency of the clock signal being output from the voltage-controlled oscillator 153 and to advance the phase of the clock signal. In contrast, when the phase of the clock signal being output from the voltage-controlled oscillator 153 goes ahead of the phase of the input pulse, the phase comparator 151 detects this lead and also decreases the voltage signal in accordance with this detected result to lower the frequency of the clock signal being output from the voltage-controlled oscillator 153 and to delay the phase of the clock signal.
When the continuously repetitive pulse is input, this PLL circuit 150 can relatively easily cause to coincide the phase of the clock signal being output from the voltage-controlled oscillator 153 with the phase of the input pulse. Therefore, this PLL circuit 150 is extensively employed in the frequency synthesizer, etc.
However, according to the phase comparator 151 constituting such PLL circuit 150, the special regard must be paid to the discontinuous pulse train with missing pulses like the tooth missing caused in the data communication when the pulse train is modulated by the data. Therefore, such PLL circuit 150 cannot attain the sufficient function and the sufficient performance as the PLL circuit.
For this reason, in the prior art, as shown in FIG. 2, the phase comparator 159 was developed (Dan H. Wolaver. Phase Locked Loop Circuit Design, p.202, Prentice Hall. ISEN 0-13-662743-9) as the phase comparator that can be applied to such discontinuous pulse train with missing pulses. This phase comparator 159 comprises two D flip-flop circuits 154, 155, one inverter circuit 156, and two exclusive-OR circuits 157, 158, and is able to directly execute the phase comparison of the discontinuous pulse train, e.g., the NRZ (Non Return to Zero)-modulated pulse.
Also, as shown in FIG. 3, the phase comparator 168 was also developed (Dan H. Wolaver, Phase Locked Loop Circuit Design, p.221, Prentice Hall, ISBN 0-13-662743-9). This phase comparator 168 comprises two D flip-flop circuits 160, 161, two exclusive-OR circuits 162, 163, and four resistors 164, 165, 166, 167, and is able to execute the phase comparison of the RZ(Return to Zero)-modulated pulse which can be obtained by previously differentiating the NRZ-modulated pulse.
FIG. 4 shows an outline of the PLL circuit 191 that employs the phase comparator 171 like the phase comparator 159 as the phase comparator 151, and the charge pump unit 172 as the low-frequency filter/amplifier 152. In this case, since the phase comparator 168 has the output waveform and the operation almost identical to those of the phase comparator 159, explanation of the PLL circuit employing this phase comparator 168 will be omitted herein.
The phase comparator 191 shown in FIG. 4 comprises the phase comparator 171 for comparing the frequency and the phase of the discontinuous pulse train Data input into the input terminal 169 with those of the clock signal Xck1 input into the input terminal 170 and also generating pulses W, X in accordance with this compared result; the charge pump unit 172 for increasing the voltage value of the voltage signal by executing the charging operation when the pulse W is output from this phase comparator 171 and also decreasing the voltage value of the voltage signal by executing the discharging operation when the pulse X is output from this phase comparator 171; and the voltage-controlled oscillator 173 for increasing the oscillating frequency as the voltage value of the voltage signal being output from this charge pump unit 172 is increased higher and also decreasing the oscillating frequency as the voltage value of the voltage signal being output from this charge pump unit 172 is decreased lower so as to generate the clock pulse Xck1. This phase comparator 191 controls the oscillating frequency of the voltage-controlled oscillator 173 such that the minimum pulse width of the discontinuous input pulse train Data can coincide with the repetitive period of the clock signal Xck1, and generates the clock signal Xck1 whose frequency is twice the maximum repetitive frequency of the discontinuous pulse train Data.
The phase comparator 171 comprises the D flip-flop circuit 174 for acquiring the pulse train Data input into the data input terminal D when the clock signal Xck1 input into the input terminal 170 rises and then outputting this pulse train Data from the output terminal Q while holding such pulse train Data; the inverter circuit 175 for inverting the clock signal Xck1 input into the input terminal the D flip-flop circuit 176 for acquiring the pulse train Data output from the output terminal Q of the D flip-flop circuit 174 from the data input terminal p when the inverted signal of the clock signal Xck1 output from this inverter circuit 175 rises and then outputting this pulse train Data from the output terminal Q while holding such pulse train Data; the exclusive-OR circuit 177 for calculating the exclusive-OR between the discontinuous pulse train Data input into the input terminal 169 and the pulse train Data output from the D flip-flop circuit 174 to generate the pulse W; and the exclusive-OR circuit 178 for calculating the exclusive-OR between the pulse train Data output from the D flip-flop circuit 174 and the pulse train Data output from the delayed flip-flop circuit 176 to generate the pulse X.
Then, as shown in (b) of FIG. 5, when the clock signal Xck1 input into the input terminal 170 rises, the D flip-flop circuit 174 is caused to acquire the pulse train Data, shown in (a) of FIG. 5, that is input into the input terminal 169 and to hold this pulse train Data. When the clock signal Xck1 input into the input terminal 170 falls and the inverted signal of the clock signal Xck1 output from the inverter circuit 175 rises, the D flip-flop circuit 176 is caused to acquire the pulse train Data that is output from the D flip-flop circuit 174 and to hold this pulse train Data. Also, in parallel with the above operations, the exclusive-OR between the pulse train Data input into the input terminal 169 and the pulse train Data output from the D flip-flop circuit 174 is calculated by the exclusive-OR circuit 177 to generate the pulse W shown in (c) of FIG. 5. Also, the exclusive-OR between the pulse train Data output from the D flip-flop circuit 174 and the pulse train Data output from the D flip-flop circuit 176 is calculated by the exclusive-OR circuit 178 to generate the pulse X shown in (d) of FIG. 5. Then, these pulses W, X are output from the output terminals 179, 180 respectively to be supplied to the input terminals 181, 182 of the charge pump unit 172.
The charge pump unit 172 comprises the inverter circuit 183 for inverting the pulse W input via the input terminal 181; the P-channel MOS transistor 184 for receiving the pulse W output from the inverter circuit 183 and for turning ON to pull up the voltage of its source terminal to the power supply voltage VDD by the power supply voltage VDD applied to its drain terminal while the pulse W is xe2x80x9c1xe2x80x9d, i.e., the pulse W is output from the output terminal 179 of the phase comparator 171; the N-channel MOS transistor 185 for receiving the pulse X input to the input terminal 182 via its gate terminal and for lowering the voltage of the drain terminal to the ground voltage xe2x80x9c0xe2x80x9d V of its source terminal while this pulse X is xe2x80x9c1xe2x80x9d; the capacitor 186 for executing the charging operation by the power supply voltage VDD generated at the source terminal of the P-channel MOS transistor 184 when the P-channel MOS transistor 184 is in its ON state and also for executing the discharging operation by the ground voltage generated at the drain terminal of the N-channel MOS transistor 185 when the N-channel MOS transistor 185 is in its ON state; the resistor 187 operated together with the capacitance of the capacitor 186 to decide the time constant of the charging/discharging operations: and the bypass capacitor 188 for attenuating a high frequency component.
Then, when the pulse W is output from the phase comparator 171 and the inverted pulse of the pulse W is output from the inverter circuit 183, the P-channel MOS transistor 184 is turned ON and then the charging/discharging circuit 189 consisting of the capacitor 186 and the resistor 187 is charged, When the pulse X is output from the phase comparator 171, the N-channel MOS transistor 185 is turned ON and then the charging/discharging circuit 189 is discharged. Thus, as shown in (e) of FIG. 5, the voltage signal is generated in accordance with an amount of charge accumulated in the capacitor 186 of the charging/discharging circuit 189, and then this voltage signal is supplied to the voltage-controlled oscillator 173 via the output terminal 190.
While increasing the oscillating frequency in compliance with the increase of the voltage value of the voltage signal output from the charge pump unit 172 and also decreasing the oscillating frequency in compliance with the decrease of the voltage value of the voltage signal, the voltage-controlled oscillator 173 feeds back the clock signal Xck1, that is obtained by the oscillating operation, to the input terminal 170 of the phase comparator 171 and also supplies this clock signal Xck1 to the succeeding stage system (not shown).
Accordingly, in this PLL circuit 191, when the phase of the clock signal Xck1 input into the input terminal 170 lags behind the phase of the discontinuous pulse train Data input into the input terminal 169, i.e., when the rise timing of the clock signal Xck1 lags behind rise/fall timings of the discontinuous pulse train Data, the width of the pulse W output from the phase comparator 171 is set wider than xe2x80x9c0.5Txe2x80x9d to expand the conduction period of the P-channel MOS transistor 184. Thus, the amount of charge accumulated in the capacitor 186 of the charging/discharging circuit 189 is increased gradually and accordingly the oscillating frequency of the voltage-controlled oscillator 173 is increased gradually.
Then, when the pulse train Data coincide in phase with the clock signal Xck1, i.e., at a point of time when the width of the pulse W output from the phase comparator 171 becomes equal to xe2x80x9c0.5Txe2x80x9d, the amount of charge accumulated in the capacitor 186 of the charging/discharging circuit 189 is kept constant and accordingly the oscillating frequency of the voltage-controlled oscillator 173 is fixed.
Then, in the situation that the pulse train Data whose pulse width is set to xe2x80x9cTxe2x80x9d is being input, when the phase of the clock signal Xck1 goes ahead of the phase of the pulse train Data, i.e., when the fall timing of the clock signal Xck1 goes ahead of the rise/fall timings of the discontinuous pulse train Data, the width of the pulse W output from the phase comparator 171 is set narrower than xe2x80x9c0.5Txe2x80x9d to shorten the conduction period of the P-channel MOS transistor 184. Thus, the amount of charge accumulated in the capacitor 186 of the charging/discharging circuit 189 is decreased gradually and accordingly the oscillating frequency of the voltage-controlled oscillator 173 is decreased gradually.
Then, when the pulse train Data coincide in phase with the clock signal Xck1, i.e., at a point of time when the width of the pulse W output from the phase comparator 171 becomes equal to xe2x80x9c0.5Txe2x80x9d, the amount of charge accumulated in the capacitor 186 of the charging/discharging circuit 189 is kept constant and accordingly the oscillating frequency of the voltage-controlled oscillator 173 is fixed. In contrast, since the exclusive-OR between the output of the D flip-flop circuit 174, that is output at the leading edge of the clock signal Xck1, and the output of the D flip-flop circuit 176, that is output substantially at the trailing edge of the clock signal Xck1 when the circuit 176 receives the output of circuit 174, is calculated, the pulse width of the pulse X is always set to 0.5T.
However, the above PLL circuit 191 in the prior art has the problems described in the following.
First, in the phase comparator 171 of the PLL circuit 191 shown in FIG. 4, the value of the pulse train Data supplied to the data input terminal D of the D flip-flop circuit 174 is received at the rise of the clock signal Xck1, and the value of the pulse train Data supplied to the data input terminal D of the D flip-flop circuit 176 (the value of the pulse train Data supplied from the data output terminal Q of the D flip-flop circuit 174) is received at the fall of the clock signal Xck1. Therefore, the pulse train Data output from the data output terminal Q of the D flip-flop circuit 176 lags behind the pulse train Data output from the data output terminal Q of the D flip-flop circuit 174 by xe2x80x9c0.5Txe2x80x9d.
For this reason, the width of the pulse W output from the exclusive-OR circuit 177 can be changed from xe2x80x9c0xe2x80x9d to xe2x80x9c1Txe2x80x9d in answer to the difference between the phase of the clock signal Xck1 and the phase of the pulse train Data, nevertheless the width of the pulse X output from the exclusive-OR circuit 178 is always kept at xe2x80x9c0.5Txe2x80x9d. That is, the width of the pulse X has merely a meaning as the reference width used to decide whether or not the width of the pulse W is shorter or longer than xe2x80x9c0.5Txe2x80x9d, on the charge pump unit 172 side.
Then, when the difference between the phase of the clock signal Xck1 and the phase of the pulse train Data is xe2x80x9c0xe2x80x9d, i.e., at a point of time when the phase coincides with each other, the widths of both the pulse W and the pulse X become xe2x80x9c0.5Txe2x80x9d. Therefore, at this time, the output can be reduced substantially to xe2x80x9c0xe2x80x9d by calculating a difference between a time-integral value of the width of the pulse W and a time-integral value of the width of the pulse X even if both the width of the pulse W and the width of the pulse X are deviated. But the problem is that occurrence times of the pulse W and the pulse X are not equal, and thus the pulsation of the voltage signal becomes large because the capacitor is charged in the period of the pulse W and is discharged in the period of the pulse X.
As the countermeasure of this, if the value of the resistor 187 and the value of the capacitor 186 both constituting the charge pump unit 172 are increased to enlarge the time constant, variation in the voltage value of the voltage signal can be reduced and thus the voltage signal can come close to the direct current. But the responsibility, especially the transient responsibility becomes worse if to do so, and therefore the value of the resistor 187 and the value of the capacitor 186 can be increased merely to some extent.
In contrast, if the value of the resistor 187 and the value of the capacitor 186 both constituting the time-constant circuit 189 are reduced to decrease the time constant, the transient responsibility can be improved, but the pulsation of the voltage value of the voltage signal is increased. Thus, the oscillating frequency of the voltage-controlled oscillator 173 is not stabilized, and there is such a possibility that the jitter, the false drawing, etc. occur.
Assume that, as particular numerical values, as shown in FIG. 6, for example, the capacitance of the capacitor 188 constituting the charge pump unit 172 is set to xe2x80x9c20 pFxe2x80x9d, the capacitance of the capacitor 186 is set to xe2x80x9c0.047 xcexcFxe2x80x9d, the power supply voltage is set to xe2x80x9c5 Vxe2x80x9d, the value of the resistor 187 is set to xe2x80x9c390 xcexa9xe2x80x9d, and the xe2x80x9c0.5Txe2x80x9d is set to xe2x80x9c5 nsxe2x80x9d, and also charging/discharging currents of the P-channel MOS transistor 184 and the N-channel MOS transistor 185 are set to xe2x80x9c200 xcexcAxe2x80x9d. Then, as shown in (e) of FIG. 5, the voltage value of the voltage signal output from the output terminal 190 of the charge pump unit 172 has the large pulsation.
In addition, if the waveform of this voltage signal is checked, the voltage value is largely varied at the portion where the pulse train Data is missed like the tooth missing. Therefore, the voltage value of the voltage signal is varied according to the pattern of the pulse train Data, and thus there is the possibility that the vicious jitter is caused,
Also, it is difficult to make the charge current of the P-channel MOS transistor 184 and the discharge current of the N-channel MOS transistor 185 equal perfectly. Thus, when any one of the P-channel KOS transistor 184 and the N-channel MOS transistor 185, e.g., the charge current of the P-channel MOS transistor 184 is slightly larger than the discharge current of the N-channel MOS transistor 185, the charge accumulated in the capacitor 186 cannot be discharged completely, as shown in (e) of FIG. 5. Therefore, although both the width of the pulse W and the width of the pulse X are xe2x80x9c0.5Txe2x80x9d, the offset is generated and the voltage value of the voltage signal is deviated from the proper value.
Such problem is the problem common to the phase comparators 171, 159, 168 (see FIG. 2, FIG. 3, and FIG. 4) in which the occurrence time of the pulse W and the occurrence time of the pulse X are different.
Also, in the phase comparator 171 employed in such PLL circuit 191, the width of the pulse W can be changed from xe2x80x9c0xe2x80x9d to xe2x80x9c1Txe2x80x9d in accordance with the difference between the phase of the clock pulse Xck1 and the phase of the pulse train Data, nevertheless the capacitor 186 of the time-constant circuit is discharged in the period of xe2x80x9c0.5Txe2x80x9d by the pulse X, that is output after the pulse W and has the width of xe2x80x9c0.5Txe2x80x9d, even after such capacitor 186 is charged in the period of xe2x80x9c1Txe2x80x9d when the width of the pulse W becomes xe2x80x9c1Txe2x80x9d. As a consequence, there is the drawback that the capacitor 186 cannot be charged up to the power supply voltage xe2x80x9cVDDxe2x80x9d and thus the output of the charge pump unit 172 cannot be increased.
Therefore, as the phase comparator to overcome the problem due to the employment of such phase comparator 171, etc. in the prior art, there is the phase comparator 192 in which the width of the pulse being output at the phase coincidence point can be set as small as possible and the occurrence time can be set to coincide with each other, as shown in FIG. 7 (Dan H. Wolaver, Phase Locked Loop Circuit Design, p.62). Such phase comparator 192 is extensively employed as the phase comparator for the continuous pulse without missing pulses.
The phase comparator 192 shown in FIG. 7 comprises the D flip-flop circuit 193 for acquiring the xe2x80x9c1xe2x80x9d signal being input into the data input terminal D every time when the differentiated pulse train Data_Dif (the pulse train obtained by differentiating the pulse train Data) is input into the clock terminal, and outputting this signal from the data output terminal Q while holding this signal, and then resetting the held content to output the xe2x80x9c0xe2x80x9d signal from the data output terminal Q every time when the xe2x80x9c1xe2x80x9d signal is input into the reset terminal R: the D flip-flop circuit 194 for acquiring the xe2x80x9c1xe2x80x9d signal input into the data input terminal D every time when the clock signal Xck1 input into the clock terminal rises, and outputting this signal from the data output terminal Q while holding this signal, and then resetting the held content to output the xe2x80x9c0xe2x80x9d signal from the data output terminal Q every time when the xe2x80x9c1xe2x80x9d signal is input into the reset terminal R; and the AND circuit 195 for generating the xe2x80x9c1xe2x80x9d signal to reset the D flip-flop circuits 193, 194 when the xe2x80x9c1xe2x80x9d signal is output from the data output terminal Q of the D flip-flop circuit 194 and also the xe2x80x9c1xe2x80x9d signal is output from the data output terminal Q of the D flip-flop circuit 193.
Then, as shown in (a) of FIG. 8, in the situation that the pulse train Data whose pulse width is set to xe2x80x9cTxe2x80x9d is supplied and also the differentiated pulse train Data_Dif obtained by differentiating the pulse train Data is input, when the phase of the differentiated pulse train Data_Dif coincides with the phase of the clock signal Xck1, as shown in (b) (c) of FIG. 8, the pulses U5, D5 that have the narrow width and are synchronized with each other are generated from the data output terminals D of the D flip-flop circuits 193, 194 respectively to cause the charge pump unit to execute the charging operation and the discharging operation, as shown in (d) (e) of FIG. 8.
However, as shown in (a) to (e) of FIG. 8, in this phase comparator 192, the excellent function can be achieved with respect to the continuous pulse train Data with no missing pulse like the pulse train Data shown in the periods A1, A2, A3, A4, A5, nevertheless the erroneous pulse (false pulse) is output as the pulse DS when the differentiated pulse train Data_Dif obtained by differentiating the pulse train Data with the missing pulse such as the pulse train Data shown in the periods B1, B2, B3, i.e., the pulse train Data with one missing pulse, the pulse train Data with two missing pulses, the pulse train Data with three missing pulses, etc. is input.
This is because the D flip-flop circuit 194 reads and outputs xe2x80x9c1xe2x80x9d at the time point of the rise of the clock signal Xck1, e.g., at the time of point P1 in FIG. 8 in the pulse missing period but the output of the D flip-flop circuit 193 has already been reset to xe2x80x9c0xe2x80x9d, thus the reset by the AND circuit 195 cannot be satisfied, thus the output of the D flip-flop circuit 194 is still kept at xe2x80x9c1xe2x80x9d until the rising time points of the succeeding differentiated pulse train Data_Dif and the clock signal Xck1, and therefore the false pulse having the wide width is output.
Accordingly, there is the drawback that such phase comparator 192 cannot handle the pulse train Data with missing pulses,
The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a phase comparator which is capable of generating a precise phase-compared output for a pulse train that is modulated by the data into the tooth missing state, minimizing ripple of a detected output to reduce as close to zero as possible when frequencies and phases coincide with each other, increasing a variable range of the detected output, reducing jitters to enable a high speed response, and having a frequency discriminating function, and a synchronizing signal extracting device using the same.
In order to achieve the above object, according to an aspect of the present invention, there is provided a phase comparator comprising: a phase comparing portion for generating a leading phase instructing pulse and a lagging phase instructing pulse to mate a phase of an input pulse train and a phase of an input clock signal with each other in accordance with the phases; a correction pulse generating portion for generating a correction pulse in accordance with the input pulse train and the input clock signal; and a resetting portion for resetting the phase comparing portion by generating a reset pulse in accordance with the leading phase instructing pulse and the lagging phase instructing pulse output from the phase comparing portion, the correction pulse output from the correction pulse generating portion, and the input clock signal.
In order to achieve the above object, according to another aspect of the present invention, there is provided a phase comparator comprising: a phase comparing portion for generating a leading phase instructing pulse and a lagging phase instructing pulse to mate a phase of an input pulse train and a phase of an input clock signal with each other in accordance with the phases; a correction pulse generating portion for generating a correction pulse in accordance with the input pulse train and the input clock signal; a resetting portion for resetting the phase comparing portion by generating a reset pulse in accordance with the leading phase instructing pulse and the lagging phase instructing pulse output from the phase comparing portion, the correction pulse output from the correction pulse generating portion, and the input clock signal; and a pulse correcting portion for removing false pulses contained in the lagging phase instructing pulse output from the phase comparing portion, based on the correction pulse output from the correction pulse generating portion.
In a preferred embodiment of the present invention, the correction pulse generating portion generates the correction pulse that has a pulse width equivalent to a time period from a time at which the correction pulse is triggered by the clock signal to a time at which the correction pulse is reset by a differentiated pulse train obtained by differentiating the pulse train, and detects a pulse missing of the input pulse train based on the pulse width of the correction pulse.
In a preferred embodiment of the present invention, the correction pulse generating portion generates the correction pulse that has a pulse width equivalent to a time period obtained by overlapping a time period from a time at which the correction pulse is triggered by the clock signal to a time at which the correction pulse is reset by a differentiated pulse train obtained by differentiating the pulse train and a time period from a time at which the correction pulse is triggered by a second clock signal that lags behind the clock signal by a predetermined degrees to a time at which the correction pulse is reset by a differentiated pulse train obtained by differentiating the pulse train, and detects a pulse missing of the input pulse train based on the pulse width of the correction pulse.
In a preferred embodiment of the present invention, the phase comparing portion includes a first flip-flop circuit triggered by a differentiated pulse train obtained by differentiating the pulse train to output the leading phase instructing pulse and a second flip-flop circuit triggered by the clock signal to output the lagging phase instructing pulse, and the resetting portion generates a reset pulse when both the leading phase instructing pulse and the lagging phase instructing pulse are output from the phase comparing portion or when the clock signal is input in a situation that the correction pulse is being output from the correction pulse generating portion, and resets the leading phase instructing pulse and the lagging phase instructing pulse by resetting the respective flip-flop circuits constituting the phase comparing portion.
In a preferred embodiment of the present invention, the phase comparing portion includes a first flip-flop circuit triggered by a differentiated pulse train obtained by differentiating the pulse train to output the leading phase instructing pulse and a second flip-flop circuit triggered by the clock signal to output the lagging phase instructing pulse, and the resetting portion generates a reset pulse when both the leading phase instructing pulse and the lagging phase instructing pulse are output from the phase comparing portion, and resets the leading phase instructing pulse and the lagging phase instructing pulse by resetting the respective flip-flop circuits constituting the phase comparing portion; or generates a reset pulse when the clock signal is input in a situation that the correction pulse is being output from the correction pulse generating portion and resets the lagging phase instructing pulse by resetting the second flip-flop circuit constituting the phase comparing portion.
In a preferred embodiment of the present invention, the phase comparing portion generates the leading phase instructing pulse and the lagging phase instructing pulse by using a differentiated pulse train obtained by differentiating both of a rise and a fall of the pulse train, and selects and outputs portions that correspond to at least one of a high level period and a low level period of the pulse train from the leading phase instructing pulse and the lagging phase instructing pulse.
In order to achieve the above object, according to still another aspect of the present invention, there is provided a synchronizing signal extracting device comprising: a phase comparator set forth in the first aspect of the present; a differentiator for differentiating an pulse train having a frequency that is xc2xd of a frequency of the Input pulse train, and supplying to the phase comparator as the input pulse train; a charge pump unit for increasing a voltage value of an output voltage signal by executing a charging operation when the leading phase instructing pulse is input from the phase comparator, and decreasing the voltage value of the output voltage signal by executing a discharging operation when the lagging phase instructing pulse is input from the phase comparator: and a voltage-controlled oscillator for receiving the voltage signal output from the charge pump unit, generating a clock signal having a frequency that increases as the voltage value of the voltage signal increases, and supplying the generated clock signal to the phase comparator.
In order to achieve the above object, according to yet still another aspect of the present invention, there is provided a synchronizing signal extracting device comprising: a phase comparator set forth in the second aspect of the present invention; a differentiator for differentiating an pulse train having a frequency that is xc2xd of a frequency of the input pulse train, and supplying to the phase comparator as the input pulse train; a charge pump unit for increasing a voltage value of an output voltage signal by executing a charging operation when the leading phase instructing pulse is input from the phase comparator, and decreasing the voltage value of the output voltage signal by executing a discharging operation when the lagging phase instructing pulse is input from the phase comparator; and a voltage-controlled oscillator for receiving the voltage signal output from the charge pump unit, generating a clock signal having a frequency that increases as the voltage value of the voltage signal increases, and supplying the generated clock signal to the phase comparator.
According to the above configurations, the precise synchronizing signal can be generated with respect to the pulse train that is brought into the tooth missing state due to a modulation by data, while reducing the number of parts. Also, the pulsation of the detected output can be minimized as small as possible to zero at the point of time when the synchronizing signal having the matched frequency and phase is obtained, and the variable range of the detected output can be expanded. As a result, the frequency variable range of the synchronizing signal can be expanded to enable the high speed response, and also the frequency discriminating function can be provided.
The nature, principle and utility of the invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings.